Ofc. I think only Swype2Wake(S2W). T2W is fail idea.t2wake gives errors and battery drain. Even in my old nexus 4. Its better to dont have it.
Ofc. I think only Swype2Wake(S2W). T2W is fail idea.t2wake gives errors and battery drain. Even in my old nexus 4. Its better to dont have it.
Is anykernel triable on wiui kk (Ivan kernel)?
No its the lastest.. I tried both but same log and same resultsTnx for log,but I think that's old version.
It should be,in case of failure be sure to post logs.
Hi all, on monday i charged my phone to 90% approx. and then, i look at the battery % and it sai 99%, so.... what? some rare facts haha.
@XperianPro I notice with your ROM and Kernel, some times whatsapp "restart", mm how can explain that.. well i never kill that app like the others, i always use home botton to minimize the app, but some times it's close alone, but i don't know, in the ivan's ROM never happen. I think the kernel kill RAM in certain time, i don't use app that kill RAM or something similar.
https://www.dropbox.com/s/iscc5l309eh644k/Screenshot_2014-08-17-16-44-25.png
(image of battery)
with any kernel support?Did you flash latest kernel maybe?
Anyway I fixed some battery issues and I will upload new kernel build today.
with any kernel support?
ThanksI don't know what's wrong with script, but when I find time I will fix it.
Did you flash latest kernel maybe?
Anyway I fixed some battery issues and I will upload new kernel build today.
The ROM is from 8/8 and the kernel from 13/8 (CM11-oc.zip)
i'll try the last ROM/kernel when you release it.
Question, if i install the las ROM i need to wipe data? format data/cache? or only cache and dalvik?
static struct acpu_level tbl_PVS0_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 900000 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 925000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 950000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 975000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 987500 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1000000 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1037500 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1062500 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1100000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1125000 },
#ifdef CONFIG_CPU_OVERCLOCK
{ 1, { 1836000, HFPLL, 1, 0x44 }, L2(14), 1150000 },
{ 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1175000 },
{ 1, { 1944000, HFPLL, 1, 0x48 }, L2(14), 1200000 },
{ 1, { 1998000, HFPLL, 1, 0x4A }, L2(14), 1225000 },
#endif
#ifdef CONFIG_OC_ULTIMATE
{ 1, { 2052000, HFPLL, 1, 0x4C }, L2(14), 1325000 },
{ 1, { 2106000, HFPLL, 1, 0x4E }, L2(14), 1325000 },
{ 1, { 2133000, HFPLL, 1, 0x4F }, L2(14), 1325000 },
{ 1, { 2160000, HFPLL, 1, 0x50 }, L2(14), 1325000 },
{ 1, { 2214000, HFPLL, 1, 0x52 }, L2(14), 1325000 },
{ 1, { 2295000, HFPLL, 1, 0x55 }, L2(14), 1325000 },
#endif
{ 0, { 0 } }
};
static struct acpu_level tbl_PVS1_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 975000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1000000 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1025000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1050000 },
#ifdef CONFIG_CPU_OVERCLOCK
{ 1, { 1836000, HFPLL, 1, 0x44 }, L2(14), 1090000 },
{ 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1120000 },
{ 1, { 1944000, HFPLL, 1, 0x48 }, L2(14), 1160000 },
{ 1, { 1998000, HFPLL, 1, 0x4A }, L2(14), 1190000 },
#endif
#ifdef CONFIG_OC_ULTIMATE
{ 1, { 2052000, HFPLL, 1, 0x4C }, L2(14), 1220000 },
{ 1, { 2106000, HFPLL, 1, 0x4E }, L2(14), 1250000 },
{ 1, { 2133000, HFPLL, 1, 0x4F }, L2(14), 1280000 },
{ 1, { 2160000, HFPLL, 1, 0x50 }, L2(14), 1310000 },
{ 1, { 2214000, HFPLL, 1, 0x52 }, L2(14), 1325000 },
{ 1, { 2295000, HFPLL, 1, 0x55 }, L2(14), 1325000 },
#endif
{ 0, { 0 } }
};
static struct acpu_level tbl_PVS2_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 987500 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1012500 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1050000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1075000 },
#ifdef CONFIG_CPU_OVERCLOCK
{ 1, { 1836000, HFPLL, 1, 0x44 }, L2(14), 1100000 },
{ 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1125000 },
{ 1, { 1944000, HFPLL, 1, 0x48 }, L2(14), 1150000 },
{ 1, { 1998000, HFPLL, 1, 0x4A }, L2(14), 1175000 },
#endif
#ifdef CONFIG_OC_ULTIMATE
{ 1, { 2052000, HFPLL, 1, 0x4C }, L2(14), 1325000 },
{ 1, { 2106000, HFPLL, 1, 0x4E }, L2(14), 1325000 },
{ 1, { 2133000, HFPLL, 1, 0x4F }, L2(14), 1325000 },
{ 1, { 2160000, HFPLL, 1, 0x50 }, L2(14), 1325000 },
{ 1, { 2214000, HFPLL, 1, 0x52 }, L2(14), 1325000 },
{ 1, { 2295000, HFPLL, 1, 0x55 }, L2(14), 1325000 },
#endif
{ 0, { 0 } }
};
static struct acpu_level tbl_PVS3_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 975000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1000000 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1025000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1050000 },
#ifdef CONFIG_CPU_OVERCLOCK
{ 1, { 1836000, HFPLL, 1, 0x44 }, L2(14), 1075000 },
{ 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1100000 },
{ 1, { 1944000, HFPLL, 1, 0x48 }, L2(14), 1125000 },
{ 1, { 1998000, HFPLL, 1, 0x4A }, L2(14), 1150000 },
#endif
#ifdef CONFIG_OC_ULTIMATE
{ 1, { 2052000, HFPLL, 1, 0x4C }, L2(14), 1250000 },
{ 1, { 2106000, HFPLL, 1, 0x4E }, L2(14), 1275000 },
{ 1, { 2133000, HFPLL, 1, 0x4F }, L2(14), 1300000 },
{ 1, { 2160000, HFPLL, 1, 0x50 }, L2(14), 1325000 },
{ 1, { 2214000, HFPLL, 1, 0x52 }, L2(14), 1325000 },
{ 1, { 2295000, HFPLL, 1, 0x55 }, L2(14), 1325000 },
#endif
{ 0, { 0 } }
};
static struct acpu_level tbl_PVS4_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 975000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1000000 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1025000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1050000 },
#ifdef CONFIG_CPU_OVERCLOCK
{ 1, { 1836000, HFPLL, 1, 0x44 }, L2(14), 1075000 },
{ 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1100000 },
{ 1, { 1944000, HFPLL, 1, 0x48 }, L2(14), 1125000 },
{ 1, { 1998000, HFPLL, 1, 0x4A }, L2(14), 1150000 },
#endif
#ifdef CONFIG_OC_ULTIMATE
{ 1, { 2052000, HFPLL, 1, 0x4C }, L2(14), 1225000 },
{ 1, { 2106000, HFPLL, 1, 0x4E }, L2(14), 1250000 },
{ 1, { 2133000, HFPLL, 1, 0x4F }, L2(14), 1275000 },
{ 1, { 2160000, HFPLL, 1, 0x50 }, L2(14), 1300000 },
{ 1, { 2214000, HFPLL, 1, 0x52 }, L2(14), 1325000 },
{ 1, { 2295000, HFPLL, 1, 0x55 }, L2(14), 1325000 },
#endif
{ 0, { 0 } }
};
static struct acpu_level tbl_PVS5_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 975000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1000000 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1025000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1050000 },
#ifdef CONFIG_CPU_OVERCLOCK
{ 1, { 1836000, HFPLL, 1, 0x44 }, L2(14), 1075000 },
{ 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1100000 },
{ 1, { 1944000, HFPLL, 1, 0x48 }, L2(14), 1125000 },
{ 1, { 1998000, HFPLL, 1, 0x4A }, L2(14), 1150000 },
#endif
#ifdef CONFIG_OC_ULTIMATE
{ 1, { 2052000, HFPLL, 1, 0x4C }, L2(14), 1200000 },
{ 1, { 2106000, HFPLL, 1, 0x4E }, L2(14), 1225000 },
{ 1, { 2133000, HFPLL, 1, 0x4F }, L2(14), 1250000 },
{ 1, { 2160000, HFPLL, 1, 0x50 }, L2(14), 1275000 },
{ 1, { 2214000, HFPLL, 1, 0x52 }, L2(14), 1300000 },
{ 1, { 2295000, HFPLL, 1, 0x55 }, L2(14), 1325000 },
#endif
{ 0, { 0 } }
};
static struct acpu_level tbl_PVS6_1700MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 975000 },
{ 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1000000 },
{ 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1025000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1050000 },
#ifdef CONFIG_CPU_OVERCLOCK
{ 1, { 1836000, HFPLL, 1, 0x44 }, L2(14), 1075000 },
{ 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1100000 },
{ 1, { 1944000, HFPLL, 1, 0x48 }, L2(14), 1125000 },
{ 1, { 1998000, HFPLL, 1, 0x4A }, L2(14), 1150000 },
#endif
#ifdef CONFIG_OC_ULTIMATE
{ 1, { 2052000, HFPLL, 1, 0x4C }, L2(14), 1175000 },
{ 1, { 2106000, HFPLL, 1, 0x4E }, L2(14), 1200000 },
{ 1, { 2133000, HFPLL, 1, 0x4F }, L2(14), 1250000 },
{ 1, { 2160000, HFPLL, 1, 0x50 }, L2(14), 1275000 },
{ 1, { 2214000, HFPLL, 1, 0x52 }, L2(14), 1300000 },
{ 1, { 2295000, HFPLL, 1, 0x55 }, L2(14), 1325000 },
#endif
{ 0, { 0 } }
};
One question.
Is it still possible to use Mokee OS or a other "standart" rom on the other partition after i repartioned with M1chas script and switched to F2FS to install Xperians Rom?
Thanks for your fast answer. I think ill give your ROM a try when im back at home next week. I would really like to undervolt my phone.
But i can still make changes with trickster mod?Its automatic now,all you need is flash kernel.
But i can still make changes with trickster mod?
and there is a method to switch back?No because /data needs to be formated to F2FS
and there is a method to switch back?
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